| 摘要 |
PURPOSE:To realize gradation processing without increasing the number of bits and at the same time to attain a compact image processor, by providing a pre-stage gradation memory between an A/D converter and an image memory together with a post-stage gradation memory set between the image memory and a D/A converter respectively. CONSTITUTION:Analog video signals are converted into l-bit digital signals by an A/D converter 1 and the (l) bits of the digital signals are converted with compression into (m) bits by a pre-stage gradation converting memory 5 synchronously with a conversion switch control signal S3. At the same time, the gradation processing is applied to the variable density of the images to be displayed. Then the converted digital signals are written in an image memory synchronously with a write/read synchronizing signal S1. The image signal read out of the memory 2 synchronously with the signal S1 is adversely converted into (n) bits from (m) bits by a post-stage gradation converting memory 6 in response to a TV synchronizing signal S2 and outputted as an analog video signal via a D/A converter 3 after gradation processing. |
