发明名称 SPEED CONTROLLER
摘要 PURPOSE:To detect the error of a frequency generator FG with improved accuracy and to correct the FG error with high accuracy by increasing the clock frequency in the detection mode of the FG error and increasing the rotational frequency of a rotor. CONSTITUTION:A clock selection means 11 has the input of clock pulses fCK1 and fCK2 and by switching these pulses with a write/read signal SRW outputs them. Then the pulse fCK1 is outputted in a read mode of a memory means 10 when fCK1<fCK2 is satisfied. While the pulse fCK2 is outputted in the write mode of the means 10. If the clock frequency is multiplied by N in a detection mode, i.e., in the write mode of the means 10, the rotational frequency of a rotor can be multiplied by N up to f0'. At the same time, the discriminating gain can be set at 1/N with the cut-off frequency multiplied by 1/N respectively. Thus a ratio N<2> is secured between the frequency f0' and the cut-off frequency with the attenuation value multiplied by 1/N<2> for the component of the frequency f0'. When an FG error is detected under such conditions, the f0' component can be set at 1/KX1/N<2>. Thus the detecting accuracy is improved with the FG error.
申请公布号 JPS63120315(A) 申请公布日期 1988.05.24
申请号 JP19860266979 申请日期 1986.11.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HASHIRANO MASARU
分类号 G05D13/62;G11B15/46;H02P23/00 主分类号 G05D13/62
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