发明名称 Arithmetic unit
摘要 Arthmetic unit for transferring the information at one bit of an accumulator or one of general registers into another bit. The accumulator comprises a first memory circuit while a flag register is used as a second memory circuit. Selection circuits for selecting the data at each bit of the first and second memory circuits are provided. When a given instruction is such that the data stored in the second memory circuit is transferred into a specified bit of the first memory circuit, only the selection circuit corresponding to the specified bit is selected so that the data stored in the second memory circuit is written, whereby the data stored in the second memory circuit is written or transferred into the specified bit of the first memory circuit.
申请公布号 US4747066(A) 申请公布日期 1988.05.24
申请号 US19840572313 申请日期 1984.01.20
申请人 TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 发明人 SUMI, MASAHIKO
分类号 G06F7/00;G06F7/76;G06F9/308;(IPC1-7):G06F7/38 主分类号 G06F7/00
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