| 摘要 |
A bus system, comprising a bus formed by a plurality of parallel lines for data transmission handshake signals and general management signals, the bus being coupled to a central processor and to a plurality of devices for transmitting and/or receiving data signals and checking signals. The system is in the data mode when the central processor is inoperative and the system is in the command mode when the central processor is operative. The bus is split into a left-hand bus half and a right-hand bus half, the series arrangement of a first interface circuit, a connecting path and a second interface circuit being arranged between the two bus halves, at least one of the interface circuits including a parallel-series-converter whose input is coupled to the associated bus half and whose output is coupled to the connecting path, the other interface including a series-parallel converter whose input is coupled to the connecting path and whose output is coupled to the associated bus half through an elastic data store, when the system is in the data mode, a device which wants to transmit data from one bus half to the other bus half will exchange the handshake signals with the interface circuit to which this device is connected through one bus half. A device connected to the other bus half through the connecting path will exchange the handshake signals with the interface circuit to which this device is connected through the other bus half.
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