发明名称 SWITCHING SYSTEM FOR MEMORY ACCESS MODE
摘要 PURPOSE:To eliminate limitation of an operand address and to control the access mode with a simple logic by using a 1-bit mode flag that can be set and reset by a specific instruction to switch the operand access modes contained in a macromode. CONSTITUTION:A main recording area is divided into a hardware area HSA and a software area SA. The area HSA stores an instruction executing procedure train which processes a specific composite instruction stored in the area SA and an instruction executing procedure train which processes a specific phenomenon if occurs. Then the addresses are discriminated at the boundary between both areas HSA and SA and a macromode MCRM flag 1 is set by logic 1 of a signal line 10 when the instruction executing procedure train stored in the area HSA is carried out. At the same time, a macromode access MCRA flag 2 instructs a main recording access mode in a macromode executing mode. Then the logic is secured between both flags 1 and 2 via an AND gate 3 and the main recording access mode is outputted to a signal line 105 in an operand access mode.
申请公布号 JPS63120336(A) 申请公布日期 1988.05.24
申请号 JP19860265502 申请日期 1986.11.10
申请人 HITACHI LTD 发明人 MORI YOSHIICHI
分类号 G06F9/22;G06F12/00;G06F12/02;G06F12/14;G06F21/02 主分类号 G06F9/22
代理机构 代理人
主权项
地址