发明名称 LOGICAL ARITHMETIC UNIT
摘要 PURPOSE:To reduce the number of program steps, by storing the result of zero checking of the result value of a logical operation other than the logical operation indicated clearly by a program. CONSTITUTION:When the exclusive OR operation of data in a work register (WR)6 and a literal value in a control storage data register (CSDR)2 is performed at a logical operation circuit 9 having an EOR function, an arithmetic result is set at the WR6 via an arithmetic result register 16. At this time, a decided result of all '0's that is the arithmetic result of the exclusive OR operation is set at an FF19, and also, the arithmetic result of a logical product not being indicated in the program, and the decided result of all '0's that is, the arithmetic result of the data in which an input data on one side is inverted, are set respectively at the FF18 and 19. Therefore, it can be said that plural logical operations are performed simultaneously from the standpoint of the program.
申请公布号 JPS63118938(A) 申请公布日期 1988.05.23
申请号 JP19860263929 申请日期 1986.11.07
申请人 HITACHI LTD 发明人 SASAKI AKIO;IGARASHI HIDEO
分类号 G06F9/26;G06F9/22 主分类号 G06F9/26
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