发明名称 BIAS IMPRESSING METHOD
摘要 PURPOSE:To eliminate ground staining at the front end part of an image by correcting a bias voltage impressed on developing rollers except the 1st one to a higher voltage while the front end part of a latent image latent image passes the developing rollers except a 1st one. CONSTITUTION:A capacitor C3 is charged with the output of a detecting circuit VD and the voltage is stored in a storage circuit M at a development time T1; and an output circuit OC determines a bias voltage corresponding to the voltage of the capacitor C3. The collector output of a transistor (TR) Q4 is generated corresponding to the input of the output circuit OC one to one and a voltage +alpha is added thereto. This +alpha is normally +40-+80V. A high voltage (+100-+200V) is impressed additionally on developing rollers 4 for a time T4 by Zener diodes Z3 and Z4. Therefore, the bias voltage impressed on the developing rollers 4 is corrected to a higher voltage until the front end part of the electrostatic latent image passes the developing rollers 4 and the induced voltage of the developing rollers by the front end part of the electrostatic latent image is detected, so a failure in applying the bias at the time of the development of the front end of the electrostatic latent image is prevented to eliminate ground staining at the image front end part.
申请公布号 JPS63118169(A) 申请公布日期 1988.05.23
申请号 JP19860264481 申请日期 1986.11.06
申请人 RICOH CO LTD 发明人 KOBAYASHI YUICHI
分类号 G03G15/06;G03G15/10 主分类号 G03G15/06
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