发明名称 ADVANCE CONTROL SYSTEM FOR INSTRUCTION ADDRESS OF INSTRUCTION PROCESSOR
摘要 PURPOSE:To simplify the circuit constitution of an instruction processor by carrying out advance of an instruction address for the instruction processor via a numerical arithmetic part of an arithmetic unit and therefore eliminating an advance circuit. CONSTITUTION:The instructions 1 and 2 are defined as a logical arithmetic instruction and a numerical arithmetic instruction respectively together with addresses of a memory defined as (n) and (n+1) respectively. The instruction 2 is read out in the next instruction step by the address (n+1) stored in an instruction address register 9 and detected to be equal to a numerical arithmetic instruction. Thus the contents of the register 9, i.e., the address (n+1) is first sent to a numerical arithmetic part 2 and stored in the register 9 after advance arithmetic prior to execution of an instruction. The data D1 is read out to a numerical arithmetic part 2 in the next instruction step and processed there. The arithmetic result data D3 calculated by an arithmetic unit 1 with both instructions 1 and 2 is sent to a designated general-purpose register.
申请公布号 JPS63118839(A) 申请公布日期 1988.05.23
申请号 JP19860264490 申请日期 1986.11.05
申请人 FUJITSU LTD 发明人 KIMURA YOSHIHIRO
分类号 G06F9/32 主分类号 G06F9/32
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