SIMULATION PROCESSOR

摘要

PURPOSE:To shorten the processing time of a simulation processor by using a means which groups the unfixed value in the time base direction at the software side and a means which recognizes these grouped values at the software side to allocate the rows of 0 and 1 to the groups of unfixed value and inputs all combinations of said groups to an actual parts. CONSTITUTION:A row of unfixed value is grouped in the time base direction in order to greatly decrease the trial frequency for '0/1' decomposition. In other words, the new logic value S is added to a software simulator to show the same signal value as the preceding one. The value S is recognized by the hardware for '0/1' decomposition to group the unfixed value X. Thus the trial frequency of the '0/1' decomposition can be reduced down to the value raised to power of 'generating frequency of unfixed value' of 2 from the conventional value raised to power of 'number of pieces of unfixed value' of 2.