| 摘要 |
PURPOSE:To reduce the hardware quantity by performing comparison arithmetic between operands with use of a fixed point addition/subtraction circuit and a conditional branch instruction executing circuit that are originally provided to an arithmetic unit. CONSTITUTION:A 1st and 2nd operand S0 and S1 stored in the 1st and 2nd operand storing registers 12 and 13 respectively are supplied to a fixed point addition/subtraction circuit 2. The circuit 2 can freely select a normal arithmetic mode or a comparison arithmetic mode in accordance with an arithmetic mode instruction signal 201 serving as the output of a decoder 5 which decodes an instruction word 4 prepared by a program. The arithmetic result S2 of the circuit 2 is led into a 3rd operand storing register 14 of a scalar register 1 via a selection circuit 11. The output S2 of the register 14 is inputted to a conditional branch instruction executing circuit 3. Then the circuit 3 carries out the branch instruction by means of a comparison condition indicating signal 301 serving as the output of the decoder 5.
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