发明名称 AUXILIARY CIRCUIT FOR RAM TEST
摘要 PURPOSE:To achieve a RAM test in a short time, by making a scan pass connected to an address terminal of a RAM able to shift bidirectionally. CONSTITUTION:It is so arranged that information given to a shift-in data terminal 9 can be scanned in synchronizing a clock given to a shift clock terminal 10. Information given to a reverse shift-in data terminal 18 also can be scanned in synchronizing a clock given to a reverse shift clock terminal 19, which provides a scan pass able to shift bidirectionally. When an address primary test is performed using a pseudo random number as address, the renewal of an address of opposite order by one clock enables a testing in a short time. To achieve this, the scan pass able to shift bidirectionally is used thereby permitting a RAM test in a short time.
申请公布号 JPS63117276(A) 申请公布日期 1988.05.21
申请号 JP19860264817 申请日期 1986.11.05
申请人 MITSUBISHI ELECTRIC CORP 发明人 MAENO HIDESHI;SAKASHITA KAZUHIRO;HANIBUCHI TOSHIAKI
分类号 G01R31/28;G11C29/00;G11C29/02;G11C29/56 主分类号 G01R31/28
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