发明名称 MEMORY INTEGRATED CIRCUIT
摘要 PURPOSE:To shorten a test time and to reduce a test cost by automatically registering a detected defect and switching it to a preliminary word line to which a preliminary memory cell having no defect is connected based on the detected result of the defect. CONSTITUTION:A detection logic output circuit 15 outputs information such as the plural presences of the defects from the output result of a detection circuit 13, a defect remedy period identifying circuit 20 starts an operation at the time of starting the defect remedy, counts the number of the integrally writing completions and the integrally comparing completions of a test pattern to all main memory cells, decides the completion of the defect remedy and an address switch 21 switches internal address information from an address counter 17 and address information inputted to a memory integrated circuit. A registration control circuit 24 controls to which defect address registering circuits 23, 23' defect address information should be registered and a main body row decoder function stopping circuit 26 constitutes a switching means together with preliminary row decoders 25, 25' to make a main body row decoder 10 inactive by receiving switching information and prohibit the selection of a word line having the defect.
申请公布号 JPS63117399(A) 申请公布日期 1988.05.21
申请号 JP19860260711 申请日期 1986.11.04
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 MATSUMURA TSUNEO;MANO TSUNEO;YAMADA JUNZO
分类号 H01L27/10;G11C11/34;G11C11/401;G11C11/407;G11C29/00;G11C29/04;H01L21/82;H01L21/822;H01L27/04 主分类号 H01L27/10
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