| 摘要 |
PURPOSE:To accelerate memory access by the reduction of wiring capacity and to reduce an unwired ratio by the drop of occupation rate of a wiring channel by increasing the degree of freedom of data in a built-in RAM on a terminal position and laying a wire from a terminal position close to a part to/from which the data are to be transmitted/received. CONSTITUTION:In case of transmitting/receiving signals to/from an I/O terminal 22 when a memory 22 has only an I/O terminal 20, the signals are transmitted/ received through a wiring 24. When an I/O terminal 21 having the same function is equipped, signal transmission/reception can be executed only through a wiring 25. In case of transmitting/receiving signals to/from a reference cell 23 when the memory 2 has only the I/O terminal 21, a wiring 26 is laid. If the I/O terminal having the same function is equipped, signal transmission/reception can be executed only through a wiring 27. Thus, the wiring length can be reduced 50% by arranging two I/O terminals. Since the acceleration of memory access can be attained and the using rate of a wiring channel can be reduced, the uncoupled rate of automatic wiring based upon a computer can be reduced and the increase of a short developing period which is the feature of a gate array LSI can be prevented by the built-in memory.
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