| 摘要 |
PURPOSE:To prevent latch-up due to a parasitic transistor by providing a CMOSIC wherein a low resistance in formed across a resistor between the parasitic transistor base and a high voltage source terminal so that the equivalent base resistance can be decreased. CONSTITUTION:A recess is formed in a semiconductor substrate 1 between the MOS-type field effect transistors of the channels different from each other constituting a CMOSIC. And on this recess, a high-concentration impurity region 23 of the same conductivity type as the semiconductor substrate is formed, a conductive electrode 24 is made on the high-concentration impurity region, and the conductive electrode 24 is connected to a power supply 20 of the CMOSIC. This result in a low resistance newly made between the high-potential power supply and the low-concentration P-type impurity region, and the parasitic resistance due to the semiconductor substrate connecting between the base and the emitter of parasitic transistor becomes equivalently small. Also, since the base width of the parasitic transistor using the semiconductor substrate as the base region become wide thereby making the current amplification factor small, the latch-up phenomenon becomes difficult to occur. |
