| 摘要 |
A digital data processing apparatus utilizes a common bus structure (42, 44, 46) for transferring information between functional units, including a processing unit (12), a peripheral control unit (20), and first and second memory units (16, 18). Unit-to-unit information transfers are executed on the bus structure by transferring signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, including a definition phase, a response phase, and a data-transfer phase, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle. The functional units are arranged for pipelining transfer cycles by transferring concurrently on the bus structure signals representative of differing phases of plural cycles. A signalling element periodically generates a first signal indicative of the necessity to refresh at least one dynamic memory element in the first memory unit. A memory refresh element normally responds to that first signal for executing a memory refresh cycle during at least one timing interval common to first and second pipelined transfer cycles. A signal is generated indicating the onset of the memory refresh cycle. A memory update element can respond to the first signal by initiating execution of a memory update cycle for transferring information from the first memory unit to the second memory unit during a timing interval common to first and second pipelined transfer cycles. The update element generates a signal indicating of the onset of the update cycle. The data processing apparatus includes a pipeline element which responds to the aforementioned onset signals for aborting further execution of said first transfer cycle while continuing the execution of said second transfer cycle. |
