| 摘要 |
PURPOSE:To send out a command and write data to a memory controller and to execute an interlock instruction by providing a means which executes the interlock instruction in a memory controller. CONSTITUTION:When a command, etc., is transferred to the final stage of a queue, a memory controller (MAC) 2 attains access to a main storage device (MS) 3 by the indication of a memory interface control part 21 according to the command (CMD) and an address (ADD) to read data in the address (ADD), so that the data is set in a read data register (DATA) 24. A comparator (C) 26 compares the read data with comparison data set in a comparison data register (CMPD) 25 and when a coincidence output is obtained, the memory interface control part 21 is actuated to write data set in a write register (DATA) 23 in an address indicated by an address register (ADD) 22. Consequently, a system bus 4 is not used exclusively and the compare and swap instruction is executed.
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