发明名称 |
CLOCK RECOVERY PHASE LOCKED LOOP CIRCUIT |
摘要 |
PURPOSE:To make the pull-in operation stable by using an analog gate circuit so as to supply phase error information to an LPF for a time of the phase error information. CONSTITUTION:The analog gate circuit 4 is interposed between an output terminal of a phase comparator circuit and an LPF 5 and an output of a T/2 pulse generating circuit 2 controls the analog gate. The T/2 pulse generating circuit 2 is started by the edge of the input signal to generate a pulse of T/2. The LPF 5 consists of a passive filter, an impedance buffer and an offset bias supply circuit. The phase error information is fed to the LPF 5 by a time having the phase information and the output of the phase synchronizing circuit is brought into a high impedance in other times. |
申请公布号 |
JPS63111725(A) |
申请公布日期 |
1988.05.17 |
申请号 |
JP19860257238 |
申请日期 |
1986.10.29 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
EJIMA NAOKI |
分类号 |
H03K5/00;G11B20/14;H03L7/08;H03L7/14 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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