| 摘要 |
A programmable clock generator includes programmable logic arrays implementing a shift register and control circuits elements connected between the inputs and outputs of the shift register elements and responsive to a code applied thereto for skipping preselected shift register elements during shifting. At least one JK flip-flop is receptive of timing signals from non-skipped shift register elements at the J and K inputs thereof to produce a clock signal at the output thereof.
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