| 摘要 |
An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the "off" interval and the other counter measures the "on" interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the "off" interval is longer than the "on" interval. Associated "hold" circuitry is operative to suspend operation of the duty cycle timer when some particular demand is satisfied, but resumes operation of the timer from where it stopped when the particular demand returns.
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