| 摘要 |
An integrated circuit including CMOS transistors and an EPROM device by a method including selectively implanting threshold adjusting atoms of P-type in the channel regions of the N-type transistors while exposing the whole device area of the P-channel transistor. Subsequently, the sources and drains of the N-channel transistors are selectively implanted using the gates as a self-aligning mask portion. The PN-junction capacitance of the sources and drains of the N-channel transistors are thereby kept low and not subject to the degrading effects of the threshold adjusting implant. The P-channel is also affected and source drain capacitances there are reduced so that the speed of all three types of transistors are enhanced. Only high-yield process steps are included.
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