发明名称 PARITY ERROR DETECTOR WITH TESTING CIRCUIT
摘要 PURPOSE:To test efficiently the operating of a circuit which makes a parity check by judging whether or not an error occurs from the contents of write data. CONSTITUTION:The write date is supplied to a RAM circuit 1 for data and a parity bit data generating circuit 2. Data read out of the circuit 1 is supplied to a parity error detecting circuit 4. The circuit 4 is supplied with the output of a RAM circuit 3 for parity bit data through a switching circuit 6. A pseudo parity bit data generating circuit 5 generates fixed data of 1 or 0, which is inputted to the circuit 4 by the circuit 6 instead of data outputted from the circuit 3 when the circuit 4 is tested. The test data is data whose number of '1's is already know and this is write data when a test is taken.
申请公布号 JPS63111477(A) 申请公布日期 1988.05.16
申请号 JP19860255828 申请日期 1986.10.29
申请人 NEC CORP 发明人 MOTOHASHI HIROYUKI
分类号 G01R31/28;G11C29/00;G11C29/42 主分类号 G01R31/28
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