| 摘要 |
<p>PURPOSE:To give a nonoverlap characteristic to an entire area in terms of a clock generator which generates multiphase clocks without overlap by inhibiting the generation of clocks with phases with the aid of a signal whose phase is different from the former and which a maximum delay route generates. CONSTITUTION:Driver parts 101 and 102 being a clock generation means are connected to a logic circuit 103 controlled by clocks T1 and T2 through respective signal lines. P1 formed at the preceding stage of the clock generator is inputted to the driver part 101, driven and transmitted to a circuit 3. Since the loads that the signal lines have are not completely capacitive but have resistance components, a waveform T1' at the point 105 of the signal line becomes duller than a waveform T1 at a point 104. Hence a signal T1' pulled out of the point 105 is inputted to the negative logic AND 7 of the driver part 102, and the nonoverlap of the clocks T2 and T1' at the points 105 and 106 is guaranteed. The same holds at points 104 and 107.</p> |
