发明名称 PREVENTING SYSTEM FOR ERROR REPERCUSSION OF COMPUTER SYSTEM IN MULTIPLE SYSTEM
摘要 PURPOSE:To surely prevent an error repercussion onto a normal computer by message of a faulty computer by throwing away a received message through the collation of result of arithmetic operation between its own computer and a sender computer. CONSTITUTION:Computer 101-103 coupled mutually by a transmission line 104 are provided with a CPU diagnostic arithmetic result storage table 105 collecting the result of CPU diagnostic arithmetic operation of all computers. If a fault takes place in a CPU, the correct result is not obtained by the CPU diagnostic arithmetic processing and a different arithmetic result from its own computer and the faulty computer is stored in the CPU arithmetic processing result storage table 105 in the normal computers. Thus, the massage sent from the faulty computer by the collation with the operating result with its own computer and the computer sending a message is all thrown away when it reaches the normal computer. Thus, no malfunction of the normal computer occurs.
申请公布号 JPS63109544(A) 申请公布日期 1988.05.14
申请号 JP19860255507 申请日期 1986.10.27
申请人 HITACHI LTD;HITACHI PROCESS COMPUT ENG INC 发明人 TEJIMA ATSUSHI;SUZUKI KATSUO;KASASHIMA HIROKAZU;KIKUCHI HISAO
分类号 G06F11/16;G06F11/18;G06F15/16 主分类号 G06F11/16
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