| 摘要 |
PURPOSE:To shorten the rise time and the test time of a system using a RAM by raising plural word lines to H level simultaneously, interrupting the current of a bit line load one of a bit line and an inverse bit line to L level and the other to H level. CONSTITUTION:When data is written in plural memory cells, a node FC is brought to H and an inverse FC to L. Transistors TrQ91, Q92 are turned on to bring the word line to H. Since an inverse C is L, a current path in which the word line is pulled down is interrupted. Since the FC is H in a current interrupting circuit 8, TrQ81, Q82 are turned off and the current of the bit line load TrQL is interrupted. At the same time, the FETQ71, Q72 of a potential fixing circuit 7 are turned on to raise the bit line to an earth level and the inverse of bit line to VCC-Vthn. In such a case, the TRQ11, Q14 of a memory cell 1 are turned on and the drain of a Q13 is precharged to -Vthn through a Q12 and data 0 is written in the memory 1. |
