| 摘要 |
PURPOSE:To reduce dispersion in the delay time of an output to each without changing the gate width of a transistor, by connecting an auxiliary multistage CMOS domino circuit to a multistage CMOS domino circuit through a program area. CONSTITUTION:The program area 7 is constituted of program wirings 8a-8d capable of connecting adjacent product terms by a program. The input of an inverter 6 which outputs product terms P1' is connected to the input of the inverter 6 outputted from the multistage CMOS domino circuit which outputs product terms P1 with the program wiring 8a. In such way, an NMOS transistor 4 consisting of the multistage CMOS domino circuit which outputs the product terms P1, and an NMOS transistor consisting of the auxiliary multistage CMOS domino circuit which outputs the product terms P1' are connected in parallel respectively, then, the gate width of each NMOS transistor can be equivalently doubled. |
