发明名称 PARALLEL CONNECTION TYPE ERROR CORRECTION SYSTEM
摘要 PURPOSE:To enable a data system to be reproduced to an original data system correctly without transmitting data after attaching a synchronizing signal from a transmission side, by attaching a code synchronizing state deciding function on plural error correction demodulators to be prepared on a reception side. CONSTITUTION:An input data system is error-correction encoded independently by using an error correction encoder 104, and its output data system is sent to a data multiplex circuit 108 via a compression buffer 106, and is multiplexed at every code block unit, then, it is transmitted. On the reception side, a trans mitted data system is separated to parallel data systems at a data separation circuit 112, and is sent to a demodulator 116 via a data expansion buffer 114. The demodulator 11b is provided with a function to decide a phase synchroniz ing state, and the data system that is the output of the demodulator 116 is multiplexed at a data multiplex circuit 120, and becomes the output data system corresponding to the input data system on the transmission side.
申请公布号 JPS63108829(A) 申请公布日期 1988.05.13
申请号 JP19860253736 申请日期 1986.10.27
申请人 KOKUSAI DENSHIN DENWA CO LTD <KDD> 发明人 YASUDA YUTAKA;HIRATA YASUO
分类号 H04L1/00;H04B1/74 主分类号 H04L1/00
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