发明名称 Clock recovery circuit
摘要 A clock recovery circuit having two inputs (Vx, Vy) for receiving the in-phase and quadrature paths respectively from a demodulator, said clock recovery circuit comprising a first module (30) which includes a phase lock loop (15) and provides an output having a spectrum line at the clock frequency, said clock recovery circuit further comprising two second clock recovery modules (31, 32), each second clock recovery module having a first input (33, 34) connected to a respective one of the two demodulated paths (Vx, Vy) and a second input (35, 36) connected to the output from the first module (30), each of said second modules comprising, in succession from said first input, a sampled threshold device (37, 38, 39, 40) for providing the sign of the signal conveyed by the corresponding path and the sign of the error, and which may be made use of by circuits for performing signal regeneration per se, a phase estimator circuit (41, 42), a filter circuit (43, 44), and a voltage controlled phase shifter circuit (45, 46) controlled by the voltage output from the filter circuit and connected to shift the phase of the signal applied to the second input (35, 36) prior to its application to the threshold circuit.
申请公布号 US4744096(A) 申请公布日期 1988.05.10
申请号 US19870004409 申请日期 1987.01.20
申请人 ALCATEL THOMSON FAISCEAUX HERTZIENS 发明人 ROUX, PIERRE
分类号 H03K5/00;H04L7/033;H04L25/40;H04L27/00;(IPC1-7):H03D3/24 主分类号 H03K5/00
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