发明名称 SYSTEM FOR CONVERTING AND CONTROL ADDRESS
摘要 PURPOSE:To reduce the frequency of TLB indexing so as to improve the processing efficiency of address conversion by continuing a page on a real memory in the course of page management. CONSTITUTION:The virtual address of an instruction to be executed is stored in the IA section 21 of a virtual address buffer 5. The IA section 24 and PA215 of a real address buffer 13 are used as a higher address with the real address corresponding to the virtual address and the LA32 of the IA section 21 of the virtual address buffer 5 is used as a lower address. The real page address is stored in the PA215 in advance. When a page cross signal 11 is outputted a control circuit 12 refers to the content of a PA113. That is to say, when the record of continuous information indicating that the pages continue in an actual memory, the signal for referring a TLB is not outputted and a value obtained by adding ''1'' to the PA215 is used as the higher actual address. In this way, TLB indexing can be omitted. On the other hand, when a record indicating that the page does not continue in an actual memory the signal for referring the TLB is outputted. Therefore, address conversion can be made at once with said continuous pages.
申请公布号 JPS59172188(A) 申请公布日期 1984.09.28
申请号 JP19830047413 申请日期 1983.03.22
申请人 FUJITSU KK 发明人 KANEDA HIROYUKI;BABA NOBUYUKI
分类号 G06F12/10 主分类号 G06F12/10
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