| 摘要 |
PURPOSE:To continue communication even in case a main station or a transmission system of the main station has a trouble, by using a digital addition circuit which adds signals after the clock phases of asynchronous clock systems are matched with each other. CONSTITUTION:A synchronous signal detecting circuit 11 detects a synchronizing signal out of the clock signal supplied to a clock input terminal 102. Then the detected synchronizing signal is delivered to a block code circuit 12, an estimating circuit 5 and a speed converting circuit 4 respectively. While a phase difference detecting circuit 3 detects the phase difference between two clock signals received from clock input terminals 102 and 202 and sends it to the circuit 4. The estimated value given from the circuit 6 is inserted into or deleted from the output signal of the circuit 12 in response to a positive-negative 360 deg. variance of said phase difference. Thus it is possible to ensure phase matching between the output signal of the circuit 4 and that of a block code circuit 22. |
