| 摘要 |
PURPOSE:To enable a test with the level sensitive scan design of a semiconductor circuit by arranging an exclusive NOR gate in front of a latch circuit in shift register constitution. CONSTITUTION:An AND gate 13 is arranged in front of a latch 12 in a test unit 11 and the clock of the latch 12 is controlled through the control line of the gate 13. Even when data is sent to the latch 12, the gate 13 does not turn on, so no data is inputted. When the output of the test unit 11 is observed, the inversion of an expected output is inputted previously to the latch circuit 6 of the shift register constitution. Then a circuit 15 is arranged in front of the clock of the circuit 6, and while the output of the test unit 11 is supplied to one input of the circuit 15, the output of the circuit 6 is supplied to the other input; when the output of the test unit 11 reaches the expected value, the value of the circuit 6 is rewritten into the expected output value and observed. Therefore, even if a fault occurs in the test unit 11 and the expected output is not outputted, the value of the circuit 6 is not rewritten, so the fault can be detected.
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