| 摘要 |
PURPOSE:To improve the processing speed of a main memory controller by writing the address of the data fetched by partial storage and the address for the next partial storage after merging both data in each other when these two addresses are equal to each other. CONSTITUTION:The address, store data and byte mark received from a CPU 0 are fetched by a memory in a partial storage mode. Then the address and the store data are supplied to address pipes 7 and 29 respectively. If a storing request is issued to an address equal to the one which is presently fetched, the store address kept waiting at an address buffer 2 is compared with the address given from the pipe 7 by a comparator 11 or 12. When coincidence is obtained between both addresses, the data on a store buffer 22 or 24 is merged with the data given from the pipe 29 by a data merging circuit 35. Furthermore the store data to be supplied to the memory functions to merge the output of the circuit 35 and the fetch data on a register 34 by a store data merging circuit 26. This merge output is set to a register 28 with addition of a bit via an ECC generator 27.
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