| 摘要 |
PURPOSE:To decrease the area of memory cell by making the gate-width of the FET of a memory cell to a specific value, and riving the latch circuit of a not-selected digit line through an activating signal, etc. CONSTITUTION:The gate-width proportion W11/W13 between the MOSFET Q11, Q13 for transfer gate of memory cells MC11, MC12,... and that W12/W14 between the MOSFET Q12, Q14 for memory-cell driving, are made a value from 0.8-1.2, and the area of a cell is made smaller. In the mean time, an activation signal supplied by a control circuit CON corresponding to a write signal and an output from a column decoder Y-DCR are logically operated; and the data latch circuit C2 and others other than those of the selected cell MC11 and others of a word line WL1 and others selected by a word drive circuit E1 and others by using an address Ax, comes in a driving status. And, even if the word line WL1 comes in the power source voltage Vcc, the data in a cell MC12 is latched by the circuit C2, is not destructed, and is written in the cell MC11 at a high speed. As a result, there will be no inconvenience occurring even when the area of a memory cell array is made smaller.
|
