发明名称 BIT LINE LEAK COMPENSATION CIRCUIT
摘要 PURPOSE:To prevent the fluctuation of a bit line precharge level by receiving a prescribed value obtained by dividing an output from an on-chip voltage conversion circuit to a gate electrode and compensating a drop in the potential of the bit line precharge level by a field effect transistor where a source voltage is connected to a bit line. CONSTITUTION:A reference potential generator circuit 2 serially connecting depression type MOSFETs QA1-QAm+n which are short-circuited with a gate and a source to attain the same potential is provided between the on-chip voltage conversion circuit 1 and a grounding. A reference potential VR taken out of a prescribed connection point is outputted to the gate electrode of a leak compensation transistor composed of an enhanced MOSFET Q1 connected to a bit line. The reference potential VR is a value obtained by resistance-dividing the potential difference between the output level VBLS of the circuit 1 and a grounding level. The number of stages (m) of the QA and (n) are set so that the VR becomes equal to the sum of a bit line precharge voltage and the threshold of the Q1. Thus a level drop in the bit line can be compensated, which is caused by the leak of P-N junction, and moreover the fluctuation of the precharge level can be prevented.
申请公布号 JPS63103497(A) 申请公布日期 1988.05.09
申请号 JP19860250513 申请日期 1986.10.20
申请人 NEC CORP 发明人 TANIGAWA TAKAO
分类号 G11C11/409;G05F3/24;G11C11/34;G11C11/407 主分类号 G11C11/409
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