| 摘要 |
PURPOSE:To reduce the cost and the arithmetic time by inputting a digital FM signal being an input to a delay device retarding it by a sample period and selecting the number of stages of the delay devices as (m) satisfying the relation of 4mf=F (f is the center frequency of the input FM signal, F is the sampling frequency and m is positive integer). CONSTITUTION:With a relation of fFM and F satisfying an equation of 4mfFM=F (fFM is the center frequency of a FM signal, F is the sampling frequency and m is a positive integer) in the delay device 2, the value (m) represents the number of unit times (1/F). In case of m=1, the equation is 4fFM=F, then the number of stages of the delay devices 2 is (1/F), and 2(1/F) in case of the relation of 8fFM=F, because m=2 is derived thereof. Then the said delayed signal is inputted to a subtracter 3 and an adder 4, the results are respectively subjected to arithmetic operation with a digital FM signal X(nT), an output of the subtracter 3 and an output of the adder 4 are subjected to absolute operation by an absolute value circuit 5, the difference between the respective outputs is subjected to arithmetic operation by the other subtracter 3, its output is given to a LPF (digital low-pass filter) 7, where the output is filtered to obtain an output signal Y(nT).
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