| 摘要 |
PURPOSE:To realize a high-speed operation by a method wherein a p-type and n-type impurity layers are formed to surround a memory circuit element section and the two conductive impurity layers are electrically connected to the output section of a substrate voltage generating circuit. CONSTITUTION:A p-type impurity layer 4 is formed on a silicon substrate 1 by selective thermal diffusion. Next, an n-type impurity layer 5 is formed by selective thermal diffusion. After these processes, or during the formation of the two conductive impurity layers, a memory circuit element section 2, substrate voltage generating circuit 3, and the like are built. The p-type impurity layer 4 and n-type impurity layer 5 are connected to the output section of the substrate voltage generating section 3 by a metal wiring 6. In this way, a negative voltage (approximately -3v) generated by the substrate voltage generating circuit 3 may be applied to a memory circuit substrate 1 through the conductive impurity layers 4 and 5 surrounding the memory circuit 2. |
