| 摘要 |
PURPOSE:To suppress the occurrence of the shift of a threshold value by interposing an impurity layer in which group III or V element is added as an impurity element to a silicon layer in a boundary between a semiconductor layer and an insulting layer. CONSTITUTION:A gate electrode 201 is patterned on a glass substrate 200, and an insulating layer 204 made, for example, of a silicon nitride (SiNx) or a silicon oxide (SiOx) is formed thereon. After an impurity layer 213 is once formed further on the layer 204, an a-Si:H semiconductor layer 205 is formed thereon, and a source electrode layer 202 and a drain electrode layer 203 are formed by interposing an n+-type a-Si:H layer 212 therebetween at an interval of suitable length. The layer 213 is formed of a p or p<+>-type, or an n or n<+>-type a-Si:H, group III element is used as an impurity dopant, in case of the P or P<+>-type, and group V element, such as a phosphorus (P) is used as an impurity dopant in case of the n or n<+>-type. |
