发明名称 EXCEPTION QUANTIZATION/COMMUNICATION SYSTEM OF DISPLAY AND CONTROL PROCESS SIGNALS
摘要 <p>A system for processing signals, and for selectively transmitting the signals to a computer and/or a display device, comprises a binary full adder (38) to add an incoming signal, in inverted form, to a previously transmitted signal to obtain the difference therebetween. A binary comparator (52) compares the difference with a predetermined value, established by thumbwheel switches (46), and if the difference exceeds the predetermined level, causes the actuation of a flip-flop (54) and a bistable latch (32) thereby the incoming signal to the transmitted to the computer and/or display device.</p>
申请公布号 JPS58207105(A) 申请公布日期 1983.12.02
申请号 JP19830044532 申请日期 1983.03.18
申请人 BABCOCK & WILCOX CO:THE 发明人 SURESHIYU SHII AGARUWARU;DAN II FUOONII;EDOWAADO DEII JIYANESEKU;MARION EI KIIZU;JIEIMUZU DEII SHIEFURAA;MAIKERU ESU UIRII
分类号 G05B15/02;G06F17/40 主分类号 G05B15/02
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