Data processor capable of immediately calculating branch address in relative address branch.

摘要

A data processor includes a data bus of N bits, an address bus of 2N bits, a memory coupled to the address bus so that a necessary information can be read from a location indicated by the address transmitted through the address bus, and first and second instruction address registers coupled to the address bus for respectively storing a less significant portion and a more significant portion of the address of an instruction to be read from the memory. An arithmetic and logic unit is coupled to the data bus and capable of adding the content of the first instruction address register and the offset contained in a relative address branch instruction so as to output the result of addition to the address bus as the lower N bits of the branch destination address. A control circuit is coupled to the arithmetic and logic unit so as to generate an increment/decrement signal on the basis of the result of addition by the arithmetic and logic unit. An increment/decrement is coupled through the data bus to the second instruction address register and controlled by the increment/decrement signal so as to increment the content of the second instruction address register when the increment signal is generated and to decrement the content of the second instruction address register when the decrement signal is generated, whereby the incrementer/decrementer outputs the incremented/decremented data to the address bus as the higher N bits of the branch destination address.