| 摘要 |
<p>Disclosed is a process for forming a planarized multilevel chip wiring structure. Starting from a substrate (30) having thereon at least a metal stud (32) serving as vertical wiring between two levels of metallization, a quartz layer (36) is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist (42) is applied. The photoresist is converted by silylation process into an organosilicate (46) having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.</p> |
