| 摘要 |
An improved electronic postage meter which includes a microcomputer (17), redundant memories ("BAMs") (35a-b), and fault flip-flops (30a-b). Improved circuitry for controlling the writing to the BAMs includes a timer ("BAM-protection timer") (40) coupled to the write-enable input of each of the BAMs. The BAM-protection timer has a trigger input (43) coupled to the microcomputer. The microcomputer is programmed to execute an instruction to generate a triggering signal at the BAM-protection timer's trigger input immediately prior to executing an instruction to write to the BAM. This opens a window for writing; the duration of the window is set to be just long enough to allow the completion of the write operation. The fault flip-flops, once set, unconditionally prevent writing to the BAMs, regardless of any other signals that might be present. The setting of the fault flip-flops is controlled by a first timer ("watchdog timer") (60) and a second timer ("second-chance timer") (62). In normal operation, the microcomputer periodically generates a trigger signal for the watchdog and second-chance timers. The watchdog interval exceeds the maximum interval between triggers under normal conditions. If a trigger is not received, the watchdog timer resets the microcomputer. The second-chance interval is longer than the watchdog interval, so that the second-chance timer times out and sets the fault flip-flops only if the restart still fails to produce a trigger signal within the specified time.
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