CMOS integrated circuit for signal delay

摘要

A CMOS integrated circuit for signal delay comprises CMOS gate circuits connected in multiple stages which deliver out an input binary signal after delaying it by a predetermined delay time. The CMOS gate circuits are arranged in a folded pattern on an integrated circuit substrate and each row of the folded pattern including a part of the CMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists of an N channel element and a P channel element cascade-connected to each other and gate patterns of the respective channels have their width and length adjusted in such a manner that value of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.