发明名称 EMPHASIZING AND DISPLAYING SYSTEM FOR SUB LINE FOR LOGIC CIRCUIT DIAGRAM
摘要 PURPOSE:To emphatically display a bus line, and to support a confirming work of logic by deciding whether each signal on a logic circuit diagram is a bus line or not, respectively, and varying its displaying method, as for the signal line which is decided to be the bus line. CONSTITUTION:When a start command is inputted, a bus line detecting part 1 checks in order from a signal line table N1, and if plural pieces of input sources of a signal line exist, and also, a type of its input sources is all a tri- state gate, its signal line is decided to be a bus line and rewrites a display attribute to red, and in other case, it is decided not to be a bus line and the display attribute remains unchanged. In case of a signal line table, signal lines N1-N5 have one piece of input source, respectively, therefore, the display attribute remains white, and a signal line N6 has plural pieces (two pieces) of input sources, and also, a type of the input sources is all a tri-state gate, therefore, it is decided to be a bus line and the display attribute is rewritten to red. Also, an for a signal line N7, its input source is one piece, therefore, the display attribute remains white.
申请公布号 JPS63100575(A) 申请公布日期 1988.05.02
申请号 JP19860245317 申请日期 1986.10.17
申请人 TOSHIBA CORP 发明人 NISHIO SEIICHI
分类号 G06F17/50 主分类号 G06F17/50
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