| 摘要 |
PURPOSE:To perform transfer of data even though an odd address of a memory is equal to a transfer start address by adding a swap buffer circuit to a direct memory access controller (DMAC). CONSTITUTION:An address ADR is supplied to a memory 23 from a current address counter 33 and at the same time the read and write control signals are supplied to the memory 23 and an I/O interface 24 respectively. Then a gate control signal and a gate control signal always kept at an H level are supplied to buffers 42 and 44. In this case, the 1-byte data read out of a memory lower-rank part 23a in an even address is supplied to an I/O interface 24 via a lower-rank data bus 21a. While the 1-byte data read out of a memory higher- rank part 23b in an odd address is supplied to the interface 24 from a higher- rank data bus 21b through a swap buffer 31 in a DMAC25 and the bus 21a. |
