发明名称 SYSTEM FOR DETECTING ERROR IN DIGITAL TRANSMISSION
摘要 PURPOSE:To detect not only a bit error during transmission but also a bit error due to stack of a specific bit of elastic storage especially by adding an error detecting code without changing the number of bits in one frame. CONSTITUTION:A receiving section extracts a frame synchronizing pulse D5 and a transmitted clock C1 from transmission data and stores this data in the elastic storage and the data stored therein is read in the timing of a control signal C6. An FF is subjected to initial set to a logical value 1 in the 3rd bit location of a time slot TS0 by a control signal C7, a parity produced by a partity generator is stored in the FF in the timing of a control signal C8 based on the initial set and the content of the 4th bit location of the time slot TS0, and the operation that the new content of the FF and the parity produced from the next bit to the transmission data are stored again in the FF is repeated until the last bit of a TS31, and the presence of an error is checked by comparing the parity bit included in the 2nd bit of the TS0 of the next frame with the content of the FF by a check device.
申请公布号 JPS59175240(A) 申请公布日期 1984.10.04
申请号 JP19830048778 申请日期 1983.03.25
申请人 HITACHI SEISAKUSHO KK 发明人 SHIMIZU KOUICHI;TAKEMURA TETSUO;GOUHARA SHINOBU;NISHIMURA KAZUO
分类号 H04L1/00;G11B20/18;H04Q11/04 主分类号 H04L1/00
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