| 摘要 |
PURPOSE:To omit the use of a mask as in a conventional method and to implement high integration density, by forming selecting gates at the side wall parts of a control gate by utilizing a side wall phenomenon, and performing self- alignment. CONSTITUTION:Formation of an insulating film 3 consisting of SiO2 and implantation of, e.g., As<+> ions, which are N-type impurities, are performed, and a source region 12 and a drain region 13 are formed. The source region 12 and the drain region 13 can be formed by self-alignment with selecting gates 8, which are side walls 11. The selecting gates 8 of the side walls 11 can be formed as follows. A gate length L is specified. A so-called dummy layer 14 is formed out of a material (e.g., SiO2 resist and the like) whose ratio with the selecting gates is different and which comprises polycrystalline Si in wet etching. Thereafter, a polycrystalline Si layer is formed on the entire surface. Anisotropic, etching by RIE is performed, and the side walls 11 comprising polycrystalline Si are formed on both sides of the dummy layer 14. The side walls 11 are made to be the selecting gates 8. |
