| 摘要 |
PURPOSE:To shorten a time detecting synchronization, by detecting a frame synchronizing signal by comparing signals in order. CONSTITUTION:A frame pattern generator 4 generates a pair of pattern codes repeatedly for 32 times to detect the pattern of the frame synchronizing signal of 12 bits, and then, generates the pattern signal of the next pair for 32 times, and generates similarly the following pair of pattern signal, thereby, the generator generates 12 pairs of pattern codes in total. In such way, the input signal of 256 bits of one frame is compared with the first pattern code of the output of the frame pattern generator 4, and a result is stored in a memory circuit 7. The output signal from the memory circuit 7 is inputted to a decision circuit 8, and synchronization detection is performed. Since the decision of 256 bits is performed by one time of detecting operation, it is possible to shorten the time of the synchronization detection. |
