| 摘要 |
PCT No. PCT/DE84/00232 Sec. 371 Date Jul. 11, 1985 Sec. 102(e) Date Jul. 11, 1985 PCT Filed Nov. 2, 1984 PCT Pub. No. WO85/02475 PCT Pub. Date Jun. 6, 1985.A method is proposed which serves to enable recognition, in microprocessors (1) provided with a monitoring device (2) having a signal generator stage for reset signals, of whether a reset signal was effected by the monitoring device (2) or by a power-on reset circuit (5). To this end, a comparison is performed between a comparison pattern stored in a non-erasable memory zone (6) and a pattern, which is typical of resetting erected by the monitoring device (2), located in an erasable memory zone (7). |
