| 摘要 |
A phase locked oscillator circuit for phase locking a clock signal to the phase of a series of sync pulses comprises a clock signal producing circuit (16) for producing a clock signal (17) having a frequency responsive to a first signal, a comparator circuit (10,12) for comparing the phase of the clock signal (17) to the phase of the series of sync pulses and producing a second clock signal (I2) responsive to the phase relation of the clock signal and the series of sync pulses, and a generator (20,22) for generating a third signal (IWB, IPK) of decreasing value during the presence of the sync pulses. A power source (18) provides a fourth signal (INB). A current mirror (26) adjusts the level of current in response to the second (I2), third (IWB, IPK) and fourth (INB) signals for producing the first signal. |
