| 摘要 |
PURPOSE:To reduce the power consumption of a boot-strap circuit and to realize the high degree of integration by performing a specific circuit forming of the said circuit of a timing generating circuit. CONSTITUTION:In a pseudo static type RAM constituted of dynamic type memory cells, its boot-strap circuit that generates a timing signal higher than the power supply voltage VCC consists of a P-type FET Q60, an N-type FET Q61 in series with the former, a CMOS inverter that receives a boot-strap start-up signal phibm, an N-type FET Q64 which the Q61 is connected with and its gate is connected with the power source, an N-type one Q62 of which gate is connected with the power source, and an N-type one Q63 in series with the former. The FETs Q60 and Q61, and those Q62 and Q63 are both formed as CMOS, and hence only either one of the CMOS is turned on. And the charge/discharge of a boot-strap capacitor CB is controlled by one of the said FETs. A through- current is prevented from occurring by the effect of the said complementary on-state of the FETs in CMOS constitution, and therefore, the power consumption is reduced. Also, the conductance characteristics of the FETs can be made irreducible because of their drive current forming, and accordingly, the circuit integration is upgraded.
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