发明名称 Method and circuit for suppressing sequential zeroes data
摘要 A method and a circuit for suppressing sequential "zeroes" data comprising, a transmitting portion and a receiving portion. The transmitting portion of the circuit provides a device for detecting whether zeroes data is sequenced in a frame, inserting the datum "1" after the sequential zeroes data when sequential zeroes data is detected, sending the frame having the datum "1" to the receiving portion and adding a portion of the frame, which is forced out by the insertion of the datum "1", to the top portion of the next frame. This forced out portion is used for detecting sequential zeroes data in the next frame. The receiving portion of the circuit detects whether the datum "1" has been inserted because sequential zeroes data are present in the frame received, and deletes the datum "1" from the received frame.
申请公布号 US4740994(A) 申请公布日期 1988.04.26
申请号 US19860863004 申请日期 1986.05.14
申请人 FUJITSU LIMITED 发明人 OUCHI, NORIAKI
分类号 H04L13/08;H04L7/02;H04L25/49;(IPC1-7):H04L27/00 主分类号 H04L13/08
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